1. Field of the Invention
The present invention relates generally to a flash memory device, and more particularly, to a system and a method for preventing read margin degradation for a nitride read only memory array.
2. Description of the Related Art
Nitride Read Only Memory (NROM) devices are widely used in the semiconductor industry. As is well known in the art, a NROM device stores charges at both ends of a composite oxide-nitride-oxide (ONO) layer, thus being capable of two bits operation. When a bit of the NROM device is programmed with a charge, the threshold voltage for that bit of the NROM device will be increased. A programmed bit of the NROM device represents a logic “0,” while an un-programmed or erased bit of the NROM device represents a logic “1.” The charge stored at one bit of the NROM device will affect the threshold voltage of the other bit, which is the second bit effect of the NROM device.
The charge retention ability of a NROM device is affected by both the cycling numbers and the aging of the NROM device. A cycling of a NROM device includes a program operation and an erase operation. As the number of cyclings for a NROM device increases, the ONO layer of the NROM device will suffer damage, thus resulting in charge losses and the decrease of the threshold voltage for the NROM device. The aging of a NROM device contributes to the charge loss as well. Therefore, the aging of a NROM device will also decrease its threshold voltage.
FIG. 1 shows the threshold voltage Vt distributions for a NROM array 100 after 10,000 cyclings and 150° C. baking for 20 hours. The high Vt distribution 110 represents the threshold voltage distribution of the NROM array 100 at a programmed state after 10,000 cyclings, whereas the low Vt distribution 130 represents the threshold voltage distribution of the NROM array 100 at an erased state after 10,000 cyclings. Each distribution has its high bond and low bond. The threshold voltage difference between the high Vt distribution 110 at its low bond and the low Vt distribution 130 at its high bond forms the read margin 150, which is the read margin for the NROM array 100 after 10,000 cyclings. No aging effect is considered for the high Vt distribution 110 and the low Vt distribution 130 of the NROM array 100.
In order to demonstrate the aging effect for the NROM array 100, after 10,000 cyclings, the NROM array 100 is baked at 150° C. for 20 hours, which is equivalent to the aging of the NROM array 100 at 25° C. for ten years. The high Vt distribution 120 represents the threshold voltage distribution for the NROM array 100 at a programmed state after 150° C. baking for 20 hours and 10,000 cyclings, whereas the low Vt distribution 140 represents the threshold voltage distribution for the NROM array 100 at an erased state after 150° C. baking for 20 hours and 10,000 cyclings. As shown, the threshold voltages of the NROM array at both the programmed state and the erase state are decreased due to the aging effect. The threshold voltage difference between the low bonds of the high Vt distributions 110 and 120 is ΔPV, while the threshold voltage difference between the high bonds of the low Vt distributions 130 and 140 is ΔEV. The threshold voltage difference between the high Vt distribution 120 at its low bond and the low Vt distribution 140 at its high bond forms the read margin 160, which is the degraded read margin for the NROM array 100 after the aging effect and 10,000 cyclings.
As indicated in FIG. 1, the read margin 160 is much narrower than the read margin 150 due to the aging effect. A narrow read margin could cause errors in a read operation for the NROM array 100. As shown, ΔPV, i.e., the decrease of the threshold voltage of the NROM array 100 at a programmed state after the NROM array 100 is affected by the aging, is the cause for the read margin degradation for the NROM array 100.
In view of the foregoing, there is a need for a system and a method that can prevent read margin degradation for a NROM array that is affected by the aging.